Differences

This shows you the differences between two versions of the page.

--- tdq:ftk [2016/06/07 14:49] – [Processor Blade] rwang
+++ tdq:ftk [2017/10/10 19:03] (current) – rwang
@@ Line 12: / Line 12: @@
 mesh ATCA backplane.
-FLIC specification {{:tdq:04022016_atlas_ftk_creat_sys_spec_1.7.2.doc|}}
+FLIC specification {{:tdq:04022016_atlas_ftk_creat_sys_spec_1.7.2.pdf|}}
-FLIC register map{{:tdq:currentflicregistermaps.pdf|}}
+FLIC register map {{:tdq:current_flic_register_maps.pdf|}}
+FLIC user manual {{:tdq:flic_user.pdf|}}
 =====FLIC production boards=====
 {{:tdq:img_20160407_215416.jpg?200|}}{{:tdq:img_20160203_151310.jpg?200|}}{{:tdq:img_20160203_151323.jpg?200|}}
@@ Line 28: / Line 29: @@
   - Each has 8 SERDES links of input from I/O processor FPGAs, matched to total ATCA output bandwidth
   - Distribute data, from the FLIC to the multiple processor blades
-{{:tdq:spybuffer.png?800|}}
   * Full, matched-bandwidth internal mesh of SERDES links between all FPGAs
 {{:tdq:internalmash.png?400|}}
@@ Line 49: / Line 49: @@
 {{:tdq:u3_u4_design_overview.pdf|}}
 {{:tdq:20150629_spy_buffer_spec.pdf|}}
+{{:tdq:spybuffer.png?800|}}
 ====Processor Blade====