Differences

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--- tdq:ftk [2016/04/15 16:14]
rwang [Shelf Manager]
+++ tdq:ftk [2016/08/04 16:23]
rwang
@@ Line 12: / Line 12: @@
 mesh ATCA backplane.
-FLIC specification {{:tdq:04022016_atlas_ftk_creat_sys_spec_1.7.2.doc|}}
+FLIC specification {{:tdq:04022016_atlas_ftk_creat_sys_spec_1.7.2.pdf|}}
-FLIC register map{{:tdq:currentflicregistermaps.pdf|}}
+FLIC register map {{:tdq:current_flic_register_maps.pdf|}}
 =====FLIC production boards=====
 {{:tdq:img_20160407_215416.jpg?200|}}{{:tdq:img_20160203_151310.jpg?200|}}{{:tdq:img_20160203_151323.jpg?200|}}
@@ Line 28: / Line 27: @@
   - Each has 8 SERDES links of input from I/O processor FPGAs, matched to total ATCA output bandwidth
   - Distribute data, from the FLIC to the multiple processor blades
-{{:tdq:spybuffer.png?800|}}
   * Full, matched-bandwidth internal mesh of SERDES links between all FPGAs
 {{:tdq:internalmash.png?400|}}
@@ Line 45: / Line 43: @@
 ==SSBe==
-=====Processor Blade=====
+=====Spy buffer=====
+The FLIC spy buffer copy the tagged events from U1&U2 to U3&U4 then assembly them into ethernet package and send to ATCA processor blade via 40Gbps ATCA back plane.
+{{:tdq:u3_u4_design_overview.pdf|}}
+{{:tdq:20150629_spy_buffer_spec.pdf|}}
+{{:tdq:spybuffer.png?800|}}
+====Processor Blade====
 The manual for the adlink processor blade 6150 at ANL{{:tdq:441142.pdf|}}.

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